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mc100es6111 rev. 5, 07/2005 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. low voltage 2.5/3.3 v differential ecl/pecl/hstl fanout buffer the mc100es6111 is a bipolar monolithic differential clock fanout buffer. designed for most demanding clock distribution systems, the mc100es6111 supports various applications that re quire distribution of precisely aligned differential clock signals. using sige:c technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. target applications for th is clock driver is high performance clock distribution in com puting, networki ng and telecomm unication systems. features ? 1:10 differential clock distribution ? 35 ps maximum device skew ? fully differential architecture from input to all outputs ? sige:c technology supports near-zero output skew ? supports dc to 2.7 ghz operation of clock or data signals ? ecl/pecl compatible differential clock outputs ? ecl/pecl/hstl compatible differential clock inputs ? single 3.3 v, ?3.3 v, 2.5 v or ?2.5 v supply ? standard 32-lead lqfp package ? 32-lead pb-free package available ? industrial temperature range ? pin and function compatible to the mc100ep111 functional description the mc100es6111 is designed for low skew clock distribution s ystems and supports clock frequencies up to 2.7 ghz. the device accepts two clock sources. the clka input can be driven by ecl or pecl compatible signals, the clkb input accepts hstl compatible signals. the selected input signal is distri buted to 10 identical, differential ecl/pecl outputs. if v bb is con- nected to the clka input and bypassed to gnd by a 10 nf capacitor, the mc100es6111 can be driven by single-ended ecl/ pecl signals utilizing the v bb bias voltage output. in order to meet the tight skew specification of the device, bot h outputs of a differential output pair should be terminated, e ven if only one output is used. in the case where not all ten outputs are used, the output pairs on the same package side as the pa rts being used on that side should be terminated. the mc100es6111 can be operated from a single 3.3 v or 2. 5 v supply. as most other ecl compatible devices, the mc100es6111 supports positive (pecl) and negative (ecl) suppl ies. the mc100es6111 is pin and function compatible to the mc100ep111. mc100es6111 low-voltage 1:10 differential ecl/pecl/hstl clock fanout driver fa suffix 32-lead lqfp package case 873a-04 ac suffix 32-lead lqfp package pb-free package case 873a-04
advanced clock drivers devices 2 freescale semiconductor mc100es6111 table 1. pin configuration pin i/o type function clka, clka input ecl/pecl differential referenc e clock signal input clkb, clkb input hstl alternative differential reference clock signal input clk_sel input ecl/pecl active clock input select q[0?9], q[0?9] output ecl/pecl differential clock outputs v ee (1) 1. in ecl mode (negative power supply mode), v ee is either ?3.3 v or ?2.5 v and v cc is connected to gnd (0 v). in pecl mode (positive power supply mode), v ee is connected to gnd (0 v) and v cc is either +3.3 v or +2.5 v. in both modes, the input and output levels are referenced to the most positive supply (v cc ). supply negative power supply v cc supply positive power supply. all v cc pins must be connected to the positive power supply for correct dc and ac operation. v bb output dc reference voltage output for single ended ecl or pecl operation table 2. function table control default 0 1 clk_sel 0 clka, clka input pair is active. clka can be driven by ecl or pecl compatible signals. clkb, clkb input pair is active. clkb can be driven by hstl compatible signals. figure 2. 32-lead package pinout (top view) q8 v cc q2 q1 q0 v cc q7 q9 q3 q3 q4 q4 q5 q5 q6 q6 v cc clk_sel clka clka v bb clkb clkb v ee 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 mc100es6111 v cc v cc q2 q1 q0 q7 q8 q9 0 1 clka clka clkb clkb clk_sel v cc v cc q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 q5 q5 q6 q6 q7 q7 q8 q8 q9 q9 v bb figure 1. mc100es6111 logic diagram
advanced clock drivers devices freescale semiconductor 3 mc100es6111 table 3. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to t he device may occur. exposure to these conditions or conditions beyond thos e indicated may adversely affect device reli ability. functional operat ion at absolute-maxim um-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.6 v v in dc input voltage ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature ?65 125 c t func functional temperature range t a = ?40 t j = +110 c table 4. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 (1) 1. output termination voltage v tt = 0 v for v cc = 2.5 v operation is supported but the power consumption of the device will increase v mm esd protection (machine model) 200 v hbm esd protection (human body model) 4000 v cdm esd protection (charged device model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ja thermal resistance junction to ambient jesd 51?3, single layer test board jesd 51?6, 2s2p multilayer test board 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 c/w c/w c/w c/w c/w c/w c/w c/w c/w c/w natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min jc thermal resistance junction to case 23.0 26.3 c/w mil-spec 883e method 1012.1 t j operating junction temperature (2) (continuous operation) mtbf = 9.1 years 2. operating junction temperature impacts device life time. ma ximum continuous operating junction temperature should be selected according to the application life time requirement s (see application note an1545 and the application section in this data sheet for more information). the device ac and dc parameters are specified up to 110 c junction temperature allowing the mc100es6111 to be used in applications requiring industrial temperature range. it is recommended that users of the mc100es6111 employ thermal modeling analysis to ass ist in applying the junction temperature specif ications to their particular application. 110 c
advanced clock drivers devices 4 freescale semiconductor mc100es6111 table 5. pecl/hstl dc characteristics (v cc = 2.5 v 5% or v cc = 3.3 v 5%, v ee = gnd, t j = 0c to +110c) symbol characteristics min typ max unit condition control input clk_sel v il input voltage low v cc ? 1.810 v cc ? 1.475 v v ih input voltage high v cc ? 1.165 v cc ? 0.880 v i in input current (1) 1. input have internal pullup/pulldown resistors which affect the input current. 100 a v in = v il or v in = v ih clock input pair clka, clka (pecl differential signals) v pp differential input voltage (2) 2. v pp (dc) is the minimum differential input voltage swing required to main tain device functionality. 0.1 1.3 v differential operation v cmr differential cross point voltage (3) 3. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when the crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. 1.0 v cc ? 0.3 v differential operation i in input current (1) 100 a v in = v il or v in = v ih clock input pair clkb, clkb (hstl differential signals) v dif differential input voltage (4) v cc = 3.3 v v cc = 2.5 v 4. v dif (dc) is the minimum differential hstl input voltage swing required for device functionality. 0.4 0.4 v v v x differential cross point voltage (5) 5. v x (dc) is the crosspoint of the differential hstl input signal. functional operation is obtained when the crosspoint is within t he v x (dc) range and the input swing lies within the v pp (dc) specification. 0 0.68 ? 0.9 v cc ? 1.1 v i in input current 200 a v in = v x 0.2 v pecl clock outputs (q0-9, q0-9 ) v oh output high voltage v cc ? 1.2 v cc ? 1.005 v cc ? 0.7 v i oh = ?30 ma (6) 6. equivalent to a termination of 50 ? to v tt . v ol output low voltage v cc = 3.3 v 5% v cc = 2.5 v 5% v cc ? 1.9 v cc ? 1.9 v cc ? 1.705 v cc ? 1.705 v cc ? 1.5 v cc ? 1.3 v i ol = ?5 ma (6) supply current and v bb i ee maximum quiescent supply current without output termination current (7) 7. i cc calculation: i cc = (number of differential output pairs used) x (i oh + i ol ) + i ee i cc = (number of differential output pairs used) x (v oh ? v tt )/r load + (v ol ? v tt )/r load + i ee 100 ma v ee pin v bb output reference voltage v cc ? 1.4 v cc ? 1.2 v i bb = 200 a
advanced clock drivers devices freescale semiconductor 5 mc100es6111 table 6. ecl dc characteristics (v ee = ?2.5 v 5% or v ee = ?3.3 v 5%, v cc = gnd, t j = 0c to +110c) symbol characteristics min typ max unit condition control input clk_sel v il input voltage low ?1.810 ?1.475 v v ih input voltage high ?1.165 ?0.880 v i in input current (1) 1. input have internal pullup/pulldown resistors which affect the input current. 100 a v in = v il or v in = v ih clock input pair clka, clka , clkb, clkb (ecl differential signals) v pp differential input voltage (2) 2. v pp (dc) is the minimum differential input voltage swing required to maintain device functionality. 0.1 1.3 v differential operation v cmr differential cross point voltage (3) 3. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when t he crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. v ee + 1.0 ?0.3 v differential operation i in input current (1) 100 a v in = v il or v in = v ih ecl clock outputs (q0-9, q0-9 ) v oh output high voltage ?1.2 ?1.005 ?0.7 v i oh = ?30 ma (4) 4. equivalent to a termination of 50 ? to v tt . v ol output low voltage v ee = ?3.3 v 5% v ee = ?2.5 v 5% ?1.9 ?1.9 ?1.705 ?1.705 ?1.5 ?1.3 v i ol = ?5 ma (4) supply current and v bb i ee maximum quiescent supply current without output termination current (5) 5. i cc calculation: i cc = (number of differential output pairs used) x (i oh + i ol ) + i ee i cc = (number of differential output pairs used) x (v oh ? v tt )/r load + (v ol ? v tt )/r load + i ee 100 ma v ee pin v bb output reference voltage v cc ? 1.4 v cc ? 1.2 v i bb = 200 a
advanced clock drivers devices 6 freescale semiconductor mc100es6111 table 7. ac characteristics (ecl: v ee = ?3.3 v 5% or v ee = ?2.5 v 5%, v cc = gnd) or (hstl/pecl: v cc = 3.3 v 5% or v cc = 2.5 v 5%, v ee = gnd, t j = 0c to +110c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition clock input pair clka, clka (pecl or ecl differential signals) v pp differential input voltage (2) (peak-to-peak) 2. v pp (ac) is the minimum differential ecl/pecl input voltage swi ng required to maintain ac characteristics including tpd and device-to-device skew. 0.15 1.3 v v cmr differential input crosspoint voltage (3) pecl 3. v cmr (ac) is the crosspoint of the differential ecl/pecl input signal . normal ac operation is obtained when the crosspoint is withi n the v cmr (ac) range and the input swing lies within the v pp (ac) specification. violation of v cmr (ac) or v pp (ac) impacts the device propagation delay, device and part-to-part skew. v ee + 1.0 v cc ? 0.3 v f clk input frequency (4) 4. the mc100es6111 is fully operational up to 3.0 ghz and is characterized up to 2.7 ghz. 2.7 ghz differential t pd propagation delay clka or clkb to q0?9 280 400 530 ps differential clock input pair clkb, clkb (hstl differential signals) v dif differential input voltage (peak-to-peak) (5) 5. v dif (ac) is the minimum differential hstl input voltage sw ing required to maintain ac characteristics including t pd and device-to-device skew. 0.4 1.0 v v x differential input crosspoint voltage (6) 6. v x (ac) is the crosspoint of the different ial hstl input signal. normal ac operation is obtained when the crosspoint is within th e v x (ac) range and the input swing lies within the v dif (ac) specification. violation of v x (ac) or v dif (ac) impacts the device propagation delay, device and part-to-part skew. v ee + 0.1 v ee + 0.68 v ee + 0.9 v ee + 2.1 v f clk input frequency 2.7 ghz differential t pd propagation delay clkb to q0-9 280 400 530 ps differential ecl clock outputs (q0-9, q0-9 ) v o(p-p) differential output voltage (peak-to-peak) f o < 300 mhz f o < 1.5 ghz f o < 2.7 ghz 0.45 0.3 0.18 0.72 0.55 0.37 0.95 0.95 0.95 v v v t sk(o) output-to-output skew 35 ps differential t sk(pp) output-to-output skew (part-to-part) f o < 1.5 ghz f o > 1.5 ghz 150 250 ps ps differential t jit(cc) output cycle-to-cycle jitter rms (1 ) 1 ps t sk(p) output pulse skew (7) 7. output pulse skew is the absolute difference of the propagation delay times: | t plh ? t phl |. 75 ps t r , t f output rise/fall time 0.05 0.3 ns 20% to 80% figure 3. mc100es6111 ac test reference differential pulse generator z = 50 ? r t = 50 ? z o = 50 ? dut mc100es6111 v tt = gnd r t = 50 ? z o = 50 ? v tt = gnd
advanced clock drivers devices freescale semiconductor 7 mc100es6111 applications information understanding the junction temperature range of the mc100es6111 to make the optimum use of high clock frequency and low skew capabilities of the mc100es6111, the mc100es6111 is specified, characterized and tested for the junction temperature range of t j = 0 c to +110 c. because the exact thermal performance depends on the pcb type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. the correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: t j = t a + r thja ? p tot assuming a thermal resistance (junction to ambient) of 54.4 c/w (2s2p board, 200 ft/min airflow, see ta b l e 4 ) and a typical power consumption of 610 mw (all outputs terminated 50 ohms to v tt , v cc = 3.3 v, frequency independent), the junction temperature of the mc100es6111 is approximately t a +33 c, and the minimum ambient temperature in this example case calculates to ?33 c (the maximum ambient temperature is 77 c, see ta b l e 8 ). exceeding the minimum junction temperature specific ation of the mc100es6111 does not have a significant impact on the device functionality. however, the continuous use of the mc100es6111 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. please see the freescale application note an1545 for a power consumption calculation guideline. maintaining lowest device skew the mc100es6111 guarantees low output-to-output bank skew of 35 ps and a part-to-part skew of max. 250 ps. to ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. when fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. if an entire output bank is not used, it is recommended to leave all of these outputs open and unte rminated. this will reduce the device power consumption while maintaining minimum output skew. power supply bypassing the mc100es6111 is a mixed analog/digital product. the differential architecture of the mc100es6111 supports low noise signal operation at high frequencies. in order to maintain its superior signal quality, all v cc pins should be bypassed by high-frequency ceramic capacitors connected to gnd. if the spectr al frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. table 8 . ambient temperature range (p tot = 610 mw) r thja (2s2p board) t a , min (1) 1. the mc100es6111 device function is guaranteed from t a = ?40c to t j = 110c t a , max natural convection 59.0c/w ?36c 74c 100 ft/min 54.4c/w ?33c 77c 200 ft/min 52.5c/w ?32c 78c 400 ft/min 50.4c/w ?30c 79c 800 ft/min 47.8c/w ?29c 81c v cc mc100es6111 v cc 33...100 nf 0.1 nf figure 4. v cc power supply bypass
advanced clock drivers devices 8 freescale semiconductor mc100es6111 package dimensions case 873a-04 issue c 32-lead lqfp package page 1 of 3
advanced clock drivers devices freescale semiconductor 9 mc100es6111 package dimensions case 873a-04 issue c 32-lead lqfp package page 2 of 3
advanced clock drivers devices 10 freescale semiconductor mc100es6111 package dimensions case 873a-04 issue c 32-lead lqfp package page 3 of 3
advanced clock drivers devices freescale semiconductor 11 mc100es6111 notes
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